Turning to FIG. 1, an example of a conventional phase lock loop (PLL) 100 can be seen. In operation, a phase/frequency detector (PFD) 102 is able to generate an up signal UP and a down signal DN for the charge pump 104 based on a comparison between a reference signal REF and a feedback signal FB. The charge pump 104 is then able to vary the charge held on low pass filter (LPF) 106 based on the signals UP and DN. The charge held on the LPF 106 can then be used by the voltage controlled oscillator (VCO) 108 to generate an output signal FOUT, and the output signal FOUT can be divided by the divider 110 to generate the feedback signal FB. As a result, the frequency of the output signal FOUT can be chosen from the reference signal REF.
Of interest here, however, is the divider 110. PLLs (like PLL 110) can be used in RF synthesizers, which can, for example, produce local oscillator signals for RF modulators, and the dividers (like divider 110) can be dynamic-logic based dividers or current mode logic dividers. As an example of a digital dynamic-logic divider that is comprised of two tri-state inverters (e.g., transistors Q1 to Q8) that are coupled in series with one another to form a ring can be seen in FIG. 2. These tri-state inverters (e.g., transistors Q1 to Q8) are coupled between voltage rails VDD and VSS and are coupled to the VCO terminals of VCO 108 so as to receive signals CLK and CLKB. These dividers, however, can have very high current consumption, which makes them impractical for low current (e.g., sub-mA) radios. Therefore, there is a need for an improved divider with lower current consumption.
An example of a conventional circuit is U.S. Pat. No. 4,119,867.